Products LEON2-MT cycle accurate simulator
The LEON2-MT cycle-accurate simulator has been derived from the LEON2-MT VHDL sources. It processes binaries generated by the slc and binutils for LEON2-MT, and generates an execution trace that is printed on the standard output. The trace shows executed processor instructions, as well as other events that appeared during program execution, such as hardware allocations, thread scheduling and cache requests. Executed memory transactions are stored in a separate file for easy inspection.