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Products - Foreground detector

Features

  • An IP core for field-programmable gate arrays.
  • Detects image foreground based on statistical processing of historical image data.
  • Uses only on-chip BRAMs. No external framebuffer required.
  • Compatible with data streaming interfaces.
  • Designed specifically to minimize resource requirements.
  • Available for resolutions from 640x480 to 1920x1080.

The foreground detector uses a statistical algorithm based on down-scaling of the resolution of a processed image while minimizing loss of information through selecting a suitable pixel aggregation. The quality of the algorithm is comparable to the Mixture-of-Gaussians algorithm for standard image datasets. The IP core was designed to use only minimum of FPGA resources.

Implementation data for XC7Z020-3CLG484

Resolution640x480704x5761280x10801920x1080
Slices1748171318851874
Slice registers1369123512601254
RAMB18E1s101040
RAMB36E1s13134566
DSP48E1s24242626
Minimum period [ns]13.91713.28313.17914.129
Running frequency [MHz]71757570
Frame rate [fps]2341855434

Application areas

Any applications that require customized feature detection or extraction, such as

  • Video surveillance
  • Access control
  • Traffic monitoring

Application example

highway_766 source highway_766 mask
A sample image from the highway dataset and the corresponding
foreground mask detected by the foreground detector IP core.

highway_766 graph
The foreground detector (SFA series) compared to the MoG algorithm (MOG series) for the highway dataset.
The graph shows foreground masks detected in time as a percentage of pixels in the whole image.

The highway dataset can be downloaded from the changedetection.net website.