LEON Floating-Point Unit

Validation

Validation of the daiFPU has been performed in these steps:

1. Validation of individual FPU modules and operations in self-checking stand-alone testbenches. Test vectors were generated using the TestFloat tool that has been developed and distributed by John Hauser.
2. Validation of the LEON2 / FPU integration using a simple C program that applies a limited number of TestFloat vectors on the FPU inputs and compares the result with a reference result stored in the TestFloat vectors.
3. Validation of the LEON2 / FPU integration using the paranoia program originally developed by Prof. Kahan.
4. Validation of correct floating-point results computed in LEON2 with daiFPU by comparing them to results of a desktop execution of an identical C program.

Availability

The daiFPU IP core is provided in the form of a synthesizable VHDL code or FPGA netlist. The IP core is available either separately or bundled together with the LEON2-FT processor. Deliverables include:

• VHDL-RTL code or gate-level netlist,
• testing environment,
• simulation scripts,
• golden reference test vectors,
• synthesis scripts,
• user documentation.

The IP core is guaranteed against defects for ninety days from the date of purchase. Thirty days of technical support over email and phone is included. Additional support and maintenance options are available.

Software Compatibility

When used with LEON processors, the daiFPU is compatible with existing compilation toolchains in the configuration DAIFPU-DUAL-DPSP that supports the same floating-point operations as other common FPUs, e.g. Meiko or GRFPU.

For other daiFPU configurations, that is those that introduce new floating-point data types and/or operations, SPARCv8 llvm compiler and binutils with daiteq extensions are required to generate binary files with the new floating-point opcodes.

Xilinx Virtex7 Implentation Results

Implementation parameters for common daiFPU configurations implemented in Xilinx Virtex7 are shown in the following table.

MicroSemi PolarFire Implentation Results

Implementation parameters for common daiFPU configurations implemented in MicroSemi PolarFire are shown in the following table.

NanoXplore NG-Medium Implentation Results

Implementation parameters for common daiFPU configurations implemented in NanoXplore NG-Medium are shown in the following table.

Floating-Point Performance

The performance of the daiteq FPU measured with the Whetstone and Linpack benchmarks is shown in the following table.

The benchmarks were compiled to test computations in the three common precisions - double, single and half (or binary64, binary32 and binary16).

Values shown in italics correspond to floating-point computations performed in software using John Hauser’s SoftFloat library (release 3e) in daiFPU configurations that do not support the corresponding precisions in hardware.

Notes:

1. Values shown in italics correspond to execution of floating-point operations in the SoftFloat library.
2. The low performance of the single-precision Whetstone benchmark computed with DAIFPU-SP (value shown in bold) is caused by the fact that single-precision trigonometric functions use double-precision operations internally to compute the approximations (e.g. the OpenLibm library).