daiteq provides arithmetic extensions for optimal computation of software-defined radio algorithms and image processing algorithms in LEON processors. Our developments cover floating-point as well as fixed-point arithmetic.
For floating-point processing in LEON processors we provide a highly configurable floating-point unit that supports all common floating-point precisions as defined in the latest IEEE 754 (2019) standard, and in addition packed floating-point formats. If needed, the FPU can be configured to an arbitrary precision before synthesis.
For fixed-point processing in LEON processors we provide custom integer ALU that supports SIMD-within-a-register operations, denoted as SWAR, that are beneficial for GNSS processing as well as audio/video processing, such as vector correlation, demodulation, addition, subtraction and multiplication for vectors of data stored in a single integer register.
Application programs can make use of our extensions through new data types that can be defined in C programs, and compiled with a LLVM compiler with daiteq extensions.
Technology demos are available for the Xilinx, Microchip and NanoXplore FPGAs.
Latest News
daiFPU vs. Meiko
How does the daiFPU compare with the Meiko FPU?
| Precision | daiFPU | Meiko |
|---|---|---|
| Whetstone | ||
| binary64 | 289 kWIPS/MHz | 283 kWIPS/MHz |
| binary32 | 324 kWIPS/MHz | 323 kWIPS/MHz |
| Linpack rolled | ||
| binary64 | 55 kFLOPS/MHz | 49 kFLOPS/MHz |
| binary32 | 72 kFLOPS/MHz | 83 kFLOPS/MHz |
| Linpack unrolled | ||
| binary64 | 59 kFLOPS/MHz | 50 kFLOPS/MHz |
| binary32 | 79 kFLOPS/MHz | 84 kFLOPS/MHz |
Date: 2020/10/09
Enhanced LEON2-FT with daiFPU and SWAR delivered to ESA
We have delivered the new leon2ft with daiFPU and SWAR extensions to ESA. The extended leon2ft will be used in future ESA missions. The delivery included synthesizable VHDL sources, testing environment, coverage data and software toolchain. Besides daiFPU and SWAR the leon2ft also features new system profiling registers.
Date: 2020/09/29