• Connects through a VITA 57.1 LPC FMC connector

• Supports 1.8V, 2.5V, 3.3V interfaces

• Can be used with the NanoXplore NG-Medium and NanoXplore NG-Large Development Kits

• Compatible with the LEON SRAM memory controller, operational at 100MHz using 2 wait states

daiFPU - Configurable Floating-Point Unit
for LEON and NOEL-V

The daiteq FPU (daiFPU) is an IEEE Std. 754 (2019) compliant floating-point unit, designed for the LEON and NOEL-V processors. The daiFPU supports binary64, binary32, binary16 formats and their combinations, including full hardware support for subnormal numbers. The unit consists of a floating-point datapath and a floating-point controller. The datapath executes all floating-point arithmetic operations and format conversions. The controller manages data exchange between the integer pipeline and the daiFPU. The controller also executes floating-point comparisons.

SWAR - SIMD-within-a-Register Arithmetic
for LEON and NOEL-V

The SIMD-within-a-register (SWAR) arithmetic extensions are targeted namely towards fixed-point applications that work with sub-word precision, e.g. 3 bits, such as satellite navigation applications, computation of neural networks in reduced integer precision or data encryption; the performance of the processor can be increased through an implementation of SIMD-like operations on variables that are stored alongside in one processor register, thus sharing the data-path circuitry for two or more operations executed in one clock cycle.

Foreground detector

The foreground detector uses a statistical algorithm based on down-scaling of the resolution of a processed image while minimizing loss of information through selecting a suitable pixel aggregation. The quality of the algorithm is comparable to the Mixture-of-Gaussians algorithm for standard image datasets. The IP core was designed to use only minimum of FPGA resources.